High-Speed Serial Link
Analysis, design, and implementation of circuit techniques for high-speed energy-efficient serial link.
Driver, Serializer, Phase-locked loop (PLL), Equalizer, Clock and data recovery (CDR), Deserializer.
Advanced Circuit Design Methodology
Develops an advanced design methodology for circuit design
PFD in NRZ 2x oversampling
PD in baud-rate sampling
Extends to develop other calibration techniques
High-Bandwidth Interface for AI Computing
Processing-in-memory
High-bandwidth and low-latency die-to-die communication
Wide I/O circuit techniques
Efficient Hardware Design Framework
Berkeley Analog Generator (BAG) is a framework for process-portable analog circuit generators
Generator-based design methodology can achieve better and faster circuit design progress
Framework for AMS circuit design provides enhanced chip design through well-established verification
Chip Gallery
48-Gb/s PAM-4 Receiver
JSSC'23
PAM-4 Receiver w/ SS-MMSE PD
Access'23
Stochastic CTLE Adaptation
TCAS-II'23
Baud-Rate CDR with Stochastic PD
ASSCC'21, JSSC'22
48-Gb/s PAM-4 Receiver
JSSC'23
PAM-4 Receiver w/ SS-MMSE PD
Access'23
Stochastic CTLE Adaptation
TCAS-II'23
Baud-Rate CDR with Stochastic PD
ASSCC'21, JSSC'22
PAM-4 TX w/ sub-sampling PLL
VLSI'22
CDR with Stochastic FPD
ISSCC'20, JSSC'22
200Gb/s PAM4 Transmitter
ISSCC'21, JSSC'22
THP-Based PAM4 Transmitter
Access'21
Injection-Locked Clock Multiplier
JSSC'21
Video Interface Receiver
TCAS-II'21
Crosstalk Cancellation for HBM
ISSCC'20
Injection-Locked PLL
TCAS-II'19
Multi-Standard Transmitter
TCAS-II'19
ILO-Based CDR
JSSC'19
Referenceless Digital CDR
VLSI'19, JSSC'21
Video Interface Receiver
VLSI'19, JSSC'20
Video Interface Receiver
TCAS-II'18
64Gb/s VCSEL Transmitter
VLSI'19
Pluggable Optics
TCAS-II'18
Video Interface Receiver
TCAS-II'17
Referenceless CDR
CICC'17, JSSC'18
Voltage-Mode Transmitter
ASSCC'15, JSSC'16, TIE'18
PLL-Based FCRX
ISCAS'15
DLL-Based FCRX
ESSCIRC'14, TCAS-I'16