Publications

2024 * Corresponding Authorship

J. Oh, K. Park*, Y.-H. Hwang*, "A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces," IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
Y. Jung, Y. Kim, S. Lee, S. Kang, and K. Park*, "A 16-30Gb/s 1.03pJ/b Referenceless Baud-Rate CDR with Integrated Pattern Decoding Technique for Fast Frequency Acquisition," IEEE Asian Solid-State Circuits Conference (ASSCC)
D. Kang, H.-G. Ko, and K. Park*, "A 3×12-Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter with Crosstalk Cancellation Technique in 28-nm CMOS," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)
S. Kang, D. Kang, S. Lee, M. Shim, S. Roh, S. Choi, and K. Park*, "A 0.09-pJ/b/dB 28-Gb/s Digital CDR with ISI-Resistant Phase Detector," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)
S. Kang, Y.-W. Kim, S. Lee, J. Kim, H. Ju, K. Lee, S. Shin, and K. Park*, "A 0.07-pJ/b/dB 32-Gb/s Receiver with Pattern-Based Baud-Rate CDR and DFE Adaptation Using 2UI Integrator without Data-Level Reference," IEEE European Solid-State Electronics Research Conference (ESSERC)
Z. Wang, M. Choi, P. Kwon, Z. Liu, B. Yin, K. Lee, K. Park, A. Biswas, J. Han, S. Du, and E. Alon, "A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS," 2024 IEEE International Symposium on Circuits and Systems (ISCAS)
S. Roh, M. Shim, Y. Jung, D.-K. Jeong, and K. Park*, "A Low-Jitter Phase Detection Technique with Asymmetric Weights in Multi-Level Baud-Rate CDR," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
M. Shim, S. Roh, Y. Lee, J.-W. Sull, D.-K. Jeong, and K. Park*, "A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
Y.-H. Hwang and K. Park*, "Analysis of Stochastic Phase-Frequency Detector in 2x Oversampling Clock and Data Recovery," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)

2023

M. Shim, W. Lee, Y. Lee, K. Park, and D.-K. Jeong, "A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver with Dead-zone Free SS-MMSE PD for CIS Link," IEEE Access
W. Jung, K. Lee, K. Park, H. Ju, J. Lee, and D.-K. Jeong, "A 48 Gb/s PAM-4 Receiver with Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS," IEEE Journal of Solid-State Circuits (JSSC)
M. Shim, K.-H. Lee, S. Roh, K. Park*, and D.-K. Jeong*, "A 1.1-pJ/b 8-to-16-Gb/s Receiver with Stochastic CTLE Adaptation," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)

2022

H. Ju, K. Lee, K. Park, W. Jung, and D.-K. Jeong, "Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector," IEEE Journal of Solid-State Circuits (JSSC)
Z. Wang, M. Choi, P. Kwon, K. Lee, B. Yin, Z. Liu, K. Park, A. Biswas, J. Han, S. Du, and E. Alon, “A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology,” 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI)
K. Park, M. Shim, H.-G. Ko, B. Nikolić, and D.-K. Jeong, “Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector,” IEEE Journal of Solid-State Circuits (JSSC)
Z. Wang, M. Choi, K. Lee, K. Park, Z. Liu, A. Biswas, J. Han, S. Du, and E. Alon, “An Output-Bandwidth-Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC)

2021

B. Kang, G.-S. Jeong, J. Hwang, K. Park, H. Do, H. Kim, H.-G. Ko, M.-C. Choi, and D.-K. Jeong, “A 10 Gb/s PAM-4 Transmitter with Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS,” IEEE Access
M.-S. Choo, S. Kim, H.-G. Ko, S.-Y. Cho, K. Park, J. Lee, S. Shin, H. Chi, and D.-K. Jeong, “A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration,” IEEE Journal of Solid-State Circuits (JSSC)
K. Park, K. Lee, S.-Y. Cho, J. Lee, J. Hwang, M.-S. Choo, and D.-K. Jeong, “A 4-20-Gb/s 1.87-pJ/b continuous-rate digital CDR circuit with unlimited frequency acquisition capability in 65-nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC)
K. Lee, H. Kim, W. Jung, J. Lee, H. Ju, K. Park, O. Kim, and D.-K. Jeong, “An adaptive offset cancellation scheme and shared-summer adaptive DFE for 0.068pJ/b/dB 1.62-to-10Gb/s low-power receiver in 40nm CMOS,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)
M. Choi, Z. Wang, K. Lee, K. Park, Z. Liu, A. Biswas, J. Han, and E. Alon, “An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS,” 2021 IEEE International Solid-State Circuits Conference (ISSCC)

2020

J. Lee, K. Lee, H. Kim, B. Kim, K. Park, and D.-K. Jeong, “A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive CTLE and DFE using biased data-level reference,” IEEE Journal of Solid-State Circuits (JSSC)
K. Park and D.-K. Jeong, “Analysis of frequency detection capability of Alexander phase detector,” Electronics Letters (EL)
K. Park, M. Shim, H.-G. Ko, and D.-K. Jeong, “A 6.4-to-32Gb/s 0.96pJ/b referenceless CDR employing ML-inspired stochastic phase-frequency detection technique in 40nm CMOS,” 2020 IEEE International Solid-State Circuits Conference (ISSCC)
H.-G. Ko, S. Shin, J. Oh, K. Park, and D.-K. Jeong, “An 8Gb/s/µm FFE-combined crosstalk-cancellation scheme for HBM on silicon interposer with 3D-staggered channels,” 2020 IEEE International Solid-State Circuits Conference (ISSCC)

2019

M.-S. Choo, Y. Song, S.-Y. Cho, H.-G. Ko, K. Park, and D.-K. Jeong, “A 15-GHz, 17.8-mW, 213-fs injection-locked PLL with maximized injection strength using adjustment of phase domain response,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)
M.-C. Choi, S.-Y. Cho, M. Shim, B. Kim, H.-G. Ko, H. Ju, K. Park, H. Kim, K. Kim, and D.-K. Jeong, “A 2.5–28 Gb/s multi-standard transmitter with two-step time-multiplexing driver,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)
G.-S. Jeong, B. Kang, H. Ju, K. Park, and D.-K. Jeong, “A Modulo-FIR equalizer for wireline communications,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
M.-S. Choo, K. Park, H.-G. Ko, S.-Y. Cho, K. Lee, and D.-K. Jeong, “A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit half-rate injection-locked CDR with path mismatch tracking loop in a 28-nm CMOS technology,” IEEE Journal of Solid-State Circuits (JSSC)
K. Park, K. Lee, S.-Y. Cho, J. Lee, J. Hwang, M.-S. Choo, and D.-K. Jeong, “A 4-to-20Gb/s 1.87pJ/b referenceless digital CDR with unlimited frequency detection capability in 65nm CMOS,” 2019 Symposium on VLSI Circuits (VLSI)
J. Lee, K. Lee, H. Kim, B. Kim, K. Park, and D.-K. Jeong, “A 0.1pJ/b/dB 1.62-to-10.8Gb/s video interface receiver with fully adaptive equalization using un-even data level,” 2019 Symposium on VLSI Circuits (VLSI)
J. Hwang, H.-S. Choi, H. Do, G.-S. Jeong, D. Koh, K. Park, and D.-K. Jeong, “A 64Gb/s 2.29pJ/b PAM-4 VCSEL transmitter with 3-tap asymmetric FFE in 65nm CMOS,” 2019 Symposium on VLSI Circuits (VLSI)

2018

K. Park, W. Bae, J. Lee, J. Hwang, and D.-K. Jeong, “A 6.7–11.2 Gb/s, 2.25 pJ/bit, single-loop referenceless CDR with multi-phase, oversampling PFD in 65-nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC)
J. Lee, K. Park, K. Lee, and D.-K. Jeong, “A 2.44-pJ/b 1.62-10-Gb/s receiver for next generation video interface equalizing 23-dB loss with adaptive 2-tap data DFE and 1-tap edge DFE,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)
G.-S. Jeong, J. Hwang, H.-S. Choi, H. Do, D. Koh, D. Yun, J. Lee, K. Park, H.-G. Ko, K. Lee, J. Joo, G. Kim, and D.-K. Jeong, “25-Gb/s clocked pluggable optics for high-density data center interconnections,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)
W. Bae, H. Ju, K. Park, J. Han, and D.-K. Jeong, “A supply-scalable serializing transmitter with controllable output swing and equalization for next generation standards,” IEEE Transactions on Industrial Electronics (TIE)

2017

K. Park, J. Lee, K. Lee, M.-S. Choo, S. Jang, S.-H. Chu, S. Kim, and D.-K. Jeong, “A 55.1 mW 1.62-to-8.1 Gb/s video interface receiver generating up to 680 MHz stream clock over 20 dB loss channel,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)
K. Park, W. Bae, and D.-K. Jeong, “A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct up/dn control,” 2017 IEEE Custom Integrated Circuits Conference (CICC)

2016

W. Bae, H. Ju, K. Park, S.-Y. Cho, and D.-K. Jeong, “A 7.6 mW, 414 fs RMS-jitter 10 GHz phase-locked loop for a 40 Gb/s serial link transmitter based on a two-stage ring oscillator in 65 nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC)
W. Bae, G.-S. Jeong, K. Park, S.-Y. Cho, Y. Kim, and D.-K. Jeong, “A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s forwarded-clock receiver with a stuck-free delay-locked loop and a half-bit delay line in 65-nm CMOS technology,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
W. Bae, H. Ju, K. Park, and D.-K. Jeong, “A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS,” 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)

2015

W. Bae, H. Ju, K. Park, S.-Y. Cho, and D.-K. Jeong, “A 7.6 mW, 214-fs RMS Jitter 10-GHz Phase-Locked Loop for 40-Gb/s Serial Link Transmitter Based on Two-Stage Ring Oscillator in 65-nm CMOS,” 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)
K. Park, W. Bae, H. Ju, J. Lee, G.-S. Jeong, Y. Kim, and D.-K. Jeong, “A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS,” 2015 IEEE International Symposium on Circuits and Systems (ISCAS)

2014

W. Bae, G.-S. Jeong, K. Park, S.-Y. Cho, Y. Kim, and D.-K. Jeong, “A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line,” 40th European Solid State Circuits Conference (ESSCIRC)
K. Park, W. Bae, and D.-K. Jeong, “A design of 5 GHz PLL as a jitter filter in forwarded clock receiver,” 2014 International Conference on Electronics, Information and Communications (ICEIC)